ADSP-214xx SHARC Processor Hardware Reference xxxvii
Contents
SRU Programming ...................................................................... 15-4
Register Overview ....................................................................... 15-5
Clocking ..................................................................................... 15-6
Choosing the Pin Enable for the SPI Clock ........................... 15-7
Functional Description ............................................................... 15-8
SPI Transaction ..................................................................... 15-9
Single Master Systems .......................................................... 15-10
Multi Master Systems .......................................................... 15-11
Operating Modes ...................................................................... 15-12
Transfer Initiate Mode ......................................................... 15-13
SPI Modes ........................................................................... 15-14
Slave Select Outputs ............................................................ 15-15
Variable Frame Delay for Slave ............................................. 15-17
Data Transfers ........................................................................... 15-18
Buffers ................................................................................ 15-18
Core Buffer Status ........................................................... 15-19
DMA Buffer Status ......................................................... 15-20
Core Transfers ..................................................................... 15-20
Backward Compatibility .................................................. 15-21
DMA Transfers ...................................... 15-21
DMA Chaining ............................................................... 15-23
DMA Transfer Count ...................................................... 15-23
Full Duplex Operation .................................................... 15-24
Interrupts ................................................................................. 15-24
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