Contents
xxxviii ADSP-214xx SHARC Processor Hardware Reference
Interrupt Sources ................................................................ 15-24
Multi Master Error .............................................................. 15-26
Debug Features ......................................................................... 15-27
Shadow Receive Buffers ....................................................... 15-27
Internal Loopback Mode ..................................................... 15-28
Loop Back Routing ......................................................... 15-28
Effect Latency .......................................................................... 15-28
Write Effect Latency ........................................................... 15-29
SPI Effect Latency ............................................................... 15-29
Programming Model ................................................................. 15-29
Changing SPI Configuration ............................................... 15-29
Master Mode Transfers ........................................................ 15-30
Core Master Transfers ..................................................... 15-31
DMA Master Transfers ................................................... 15-31
Slave Mode Transfers ........................................................... 15-32
Core Slave Transfers ........................................................ 15-32
DMA Slave Transfers ...................................................... 15-33
Chained DMA Transfers ..................................................... 15-33
Stopping SPI Transfers ........................................................ 15-33
Switching From Transmit to a New DMA ............................ 15-34
Switching From Receive to a New DMA .............................. 15-35
DMA Error Interrupts ......................................................... 15-37
Multi-Master Transfers ................................................... 15-38
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