Analog Devices SHARC ADSP-214 Series - Page 43

ADSP-214xx SHARC Processor Hardware Reference xliii
Contents
UART Effect Latency .......................................................... 20-21
Programming Model ................................................................. 20-21
Autobaud Detection ............................................................ 20-21
Programming Model for DMA Transfers .............................. 20-22
Setting Up and Starting Chained DMA ........................... 20-22
Notes on Using UART DMA .......................................... 20-23
Programming Model for Core Transfers ................................ 20-24
TWO WIRE INTERFACE CONTROLLER
Features ...................................................................................... 21-2
Pin Descriptions ......................................................................... 21-3
SRU Programming ...................................................................... 21-4
Clocking ..................................................................................... 21-4
Register Overview ....................................................................... 21-5
Functional Description ............................................................... 21-6
Bus Arbitration ..................................................................... 21-9
Start and Stop Conditions ................................................... 21-10
Slave Mode Addressing ........................................................ 21-11
Master Mode Addressing ..................................................... 21-11
Data Transfer ............................................................................ 21-12
Data Buffers ........................................................................ 21-12
8-Bit Transmit FIFO Register .......................................... 21-12
16-Bit Transmit FIFO Register ........................................ 21-12
8-Bit Receive FIFO Register ............................................ 21-13
16-Bit Receive FIFO Register .......................................... 21-14
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