Operating Modes
16-14 ADSP-214xx SHARC Processor Hardware Reference
The count registers are reset to 0x0000 0001 again, and the timer contin-
ues counting until it is either disabled or the count value reaches
0xFFFF FFFF.
In this mode, programs can measure both the pulse width and the pulse
period of a waveform. To control the definition of the leading edge and
trailing edge of the
TIMERx_I signal, the PULSE bit in the TMxCTL register is
set or cleared. If the PULSE bit is cleared, the measurement is initiated by a
falling edge, the count register is captured to the WIDTH register on the ris-
ing edge, and the period register is captured on the next falling edge.
The PRDCNT bit in the TMxCTL register controls whether an enabled inter-
rupt is generated when the pulse width or pulse period is captured. If the
PRDCNT bit is set, the interrupt latch bit (TIMxIRQ) gets set when the pulse
period value is captured. If the PRDCNT bit is cleared, the TIMxIRQ bit gets
set when the pulse width value is captured.
If the PRDCNT bit is cleared, the first period value has not yet been mea-
sured when the first interrupt is generated. Therefore, the period value is
not valid. If the interrupt service routine reads the period value anyway,
the timer returns a period value of zero. When the period expires, the
period value is loaded in the TMxPRD register.
A timer interrupt (if enabled) is also generated if the count register reaches
a value of 0xFFFF FFFF. At that point, the timer is disabled automati-
cally, and the
TIMxOVF status bit is set, indicating a count overflow. The
TIMxIRQ and TIMxOVF bits are sticky bits, and programs must explicitly
clear them. The WDTH_CAP timing is shown in Figure 16-6.
The first width value captured in WDTH_CAP mode is erroneous due to
synchronizer latency. To avoid this error, programs must issue two
NOP
instructions between setting WDTH_CAP mode and setting
TIMxEN.
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