Analog Devices SHARC ADSP-214 Series - Page 945

ADSP-214xx SHARC Processor Hardware Reference A-119
Registers Reference
Figure A-53. SRU_CLK1 Register (RW)
Figure A-54. SRU_CLK2 Register (RW)
SRC2_CLK_OP_I (29–25)
SRC1_CLK_OP_I (19–15)
SRC2_CLK_IP_I (24–20)
SRC1_CLK_OP_I (19–15)
SRC1_CLK_IP_I (14–10)
SRC0_CLK_OP_I (9–5)
SRC0_CLK_IP_I (4–0)
Sample Rate Converter 2
Clock Output Input
Sample Rate Converter 1
Clock Output Input
Sample Rate Converter 2
Clock Input Input
Sample Rate Converter 1
Clock Output Input
Sample Rate Converter 0
Clock Input Input
Sample Rate Converter 0
Clock Output Input
Sample Rate Converter 1
Clock Input Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
IDP2_CLK_I (29–25)
Input Data Port 2 Clock Input
IDP0_CLK_I (con’t) (19–15)
Input Data Port 0 Clock Input
DIT_CLK_I (14–10)
SRC3 _CLK_IP_I (4–0)
SRC3_CLK_OP_I (9–5)
IDP0_CLK_I (19–15)
IDP1_CLK_I (24–20)
Input Data Port 1 Clock Input
Sample Rate Converter 3
Clock Input Input
SPDIF Transmitter Clock Input
Sample Rate Converter 3 Clock Output Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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