Analog Devices SHARC ADSP-214 Series

DAI Signal Routing Unit Registers
A-120 ADSP-214xx SHARC Processor Hardware Reference
Figure A-55. SRU_CLK3 Register (RW)
Figure A-56. SRU_CLK4 Register (RW)
DIT_HFCLK_I (29–25)
IDP6_CLK_I (con’t) (19–15)
IDP7_CLK_I (24–20)
IDP6_CLK_I (19–15)
IDP5_CLK_I (14–10)
IDP3_CLK_I (4–0)
IDP4_CLK_I (9–5)
Input Data Port Channel
6 Clock Input
SPDIF Oversampling Clock Input
Input Data Port Channel
3 Clock Input
Input Data Port Channel
4 Clock Input
Input Data Port Channel
7 Clock Input
Input Data Port Channel 5 Clock Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
SPDIF_EXTPLLCLK_I (14–10)
External 512 x FS PLL Clock Input
PCG_EXTA_I (4–0)
Precision Clock Generator
External Clock A Input
PCG_EXTB_I (9–5)
Precision Clock Generator
External Clock B Input
PCG_SYNC_CLKB_I (29–25)
Precision Clock Generator
Clock B Sync Input
PCG_SYNC_CLKA_I
Precision Clock Generator
Clock A Sync Input
DIT_EXT_SYNC_I (19–15)
DIT_EXT_SYNC_I (19–15)
S/PDIF Transmitter Clock
Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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