ADSP-214xx SHARC Processor Hardware Reference A-121
Registers Reference
Figure A-57. SRU_CLK5 Register (RW)
Table A-75. Group A Sources – Serial Clock
Selection Code Source Signal Description (Source Selection)
00000 (0x0) DAI_PB01_O Pin Buffer 1
00001 (0x1) DAI_PB02_O Pin Buffer 2
00010 (0x2) DAI_PB03_O Pin Buffer 3
00011 (0x3) DAI_PB04_O Pin Buffer 4
00100 (0x4) DAI_PB05_O Pin Buffer 5
00101 (0x5) DAI_PB06_O Pin Buffer 6
00110 (0x6) DAI_PB07_O Pin Buffer 7
00111 (0x7) DAI_PB08_O Pin Buffer 8
01000 (0x8) DAI_PB09_O Pin Buffer 9
01001 (0x9) DAI_PB10_O Pin Buffer 10
01010 (0xA) DAI_PB11_O Pin Buffer 11
01011 (0xB) DAI_PB12_O Pin Buffer 12
01100 (0xC) DAI_PB13_O Pin Buffer 13
PCG_SYNC_CLKC_I
Precision Clock Generator
Clock C Sync Input
SPORT6_CLK_I
Serial Port 6 Clock Input
SPORT7_CLK_I
Serial Port 7 Clock Input
PCG_SYNC_CLKD_I
Precision Clock Generator
Clock D Sync Input
PCG_EXTC_I
PCG_SYNC_CLKD_I
Precision Clock Generator
External Clock C Input
PCG_EXTD_I
Precision Clock Generator
External Clock D Input
Precision Clock Generator
Clock D Sync Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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