DPI Signal Routing Unit Registers
A-228 ADSP-214xx SHARC Processor Hardware Reference
Figure A-129. SRU2_PBEN2 Register
Table A-120. Group C Signals
Binary Signal Description (Source Selection)
000000 (0x0) LOW Logic Level Low (0)
000001 (0x1) HIGH Logic Level High (1)
000010 (0x2) MISCB0_O Miscellaneous Control 0
000011 (0x3) MISCB1_O Miscellaneous Control 1
000100 (0x4) MISCB2_O Miscellaneous Control 2
000101 (0x5) TIMER0_PBEN_O Enable for Timer 0 Output
000110 (0x6) TIMER1_PBEN_O Enable for Timer 1 Output
000111 (0x7) Reserved
001000 (0x8) UART0_TX_PBEN_0 Pin Enable for UART 0 Transmitter
001001 (0x9) Reserved
001010 (0xA) SPIMISO_PBEN_O Pin Enable for MISO from SPI
001011 (0xB) SPIMOSI_PBEN_O Pin Enable for MOSI from SPI
001100 (0xC) SPICLK_PBEN_O Pin Enable for CLK from SPI
001101 (0xD) SPIFLG0_PBEN_O Pin Enable for Slave Select 0 from SPI
001110 (0xE) SPIFLG1_PBEN_O Pin Enable for Slave Select 1 from SPI
001111 (0xF) SPIFLG2_PBEN_O Pin Enable for Slave Select 2 from SPI
DPI_PBEN13_I (17–12) con’t
DPI Pin Buffer Enable 13
Input
DPI_PBEN14_I (23–18)
DPI Pin Buffer Enable 14 Input
DPI_PBEN13_I (17–12)
DPI_PBEN12_I (11–6)
DPI Pin Buffer Enable 12 Input
DPI_PBEN11_I (5–0)
DPI Pin Buffer Enable 11
Input
DPI Pin Buffer Enable 13 Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
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