Peripherals Routed Through the DPI
A-266 ADSP-214xx SHARC Processor Hardware Reference
Figure A-153. TWIIRPTL Register
Table A-144. TWIIRPTL Register Bit Descriptions (W1X)
Bit Name Description
0 TWISINIT Slave Transfer Initiated.
0 = A transfer is not in progress. An address match has not occurred
since the last time this bit was cleared.
1 = The slave has detected an address match and a transfer has been
initiated.
1TWISCOMP Slave Transfer Complete.
0 = The completion of a transfer not detected
1 = The transfer is complete and either a stop, or a restart was
detected.
2TWISERR Slave Transfer Error.
0 = No errors detected
1 = An error has occurred. A restart or stop condition has occurred
during the data receive phase of a transfer.
3TWISOVF Slave Overflow.
0 = No overflow detected
1 = The slave transfer complete (TWISCOMP) was set at the time a
subsequent transfer has acknowledged an address phase. The transfer
continues, however, it may be difficult to delineate data of one trans-
fer from another.
4TWIMCOM Master Transfer Complete.
0 = The completion of a transfer not detected
1 = The initiated master transfer is complete. In the absence of a
repeat start, the bus is released.
TWISINIT
TWISCOMP
TWISERR
TWISOVF
TWIRXINT
TWITXINT
TWIMERR
TWIMCOM
Slave Transfer Initiated
Slave Transfer Complete
Slave Transfer Error
Slave Overflow
Receive FIFO Service
Transmit FIFO Service
Master Transfer Error
Master Transfer Complete
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