Peripherals Routed Through the DPI
A-272 ADSP-214xx SHARC Processor Hardware Reference
5 (RO) TIM1OVF Timer 1 Overflow/Error Also an output
7–6 Reserved
8 TIM0EN Timer 0 Enable Enable timer 0
9 (W1C) TIM0DIS Timer 0 Disable Disable timer 0
10 TIM1EN Timer 1 Enable Enable timer 1
Table A-147. TMxSTAT Register Bit Descriptions (RW) (Cont’d)
Bit Name Description