Register Listing
A-276 ADSP-214xx SHARC Processor Hardware Reference
SPCTLN1 0xC1B SPORT 1 Control Register 2 0x0000 0000
DIV0 0xC02 SPORT 0 Divisor for TX/RX SCLK0 and FS0 0x0
DIV1 0xC03 SPORT 1 Divisor for TX/RX SCLK1 and FS1 0x0
SPMCTL0 0xC04 SPORT 0 TDM Control Register 0x0
SPMCTL1 0xC17 SPORT 1 TDM Control Register 0x0
MT0CS0 0xC05 SPORT 0 TDM TX Select, CH31–0 0x0
MT0CS1 0xC06 SPORT 0 TDM TX Select, CH63–32 0x0
MT0CS2 0xC07 SPORT 0 TDM TX Select, CH95–64 0x0
MT0CS3 0xC08 SPORT 0 TDM TX Select, CH127–96 0x0
MR1CS0 0xC09 SPORT 1 TDM RX Select, CH31–0 0x0
MR1CS1 0xC0A SPORT 1 TDM RX Select, CH63–32 0x0
MR1CS2 0xC0B SPORT 1 TDM RX Select, CH95–64 0x0
MR1CS3 0xC0C SPORT 1 TDM RX Select, CH127–96 0x0
MT0CCS0 0xC0D SPORT 0 TDM TX Compand Select, CH31–0 0x0
MT0CCS1 0xC0E SPORT 0 TDM TX Compand Select, CH63–32 0x0
MT0CCS2 0xC0F SPORT 0 TDM TX Compand Select, CH95–64 0x0
MT0CCS3 0xC10 SPORT 0 TDM TX Compand Select, CH127–96 0x0
MR1CCS0 0xC11 SPORT 1 TDM RX Compand Select, CH31–0 0x0
MR1CCS1 0xC12 SPORT 1 TDM RX Compand Select, CH63–32 0x0
MR1CCS2 0xC13 SPORT 1 TDM RX Compand Select, CH95–64 0x0
MR1CCS3 0xC14 SPORT 1 TDM RX Compand Select, CH127–96 0x0
IISP0A 0xC40 Internal Memory DMA Address 0x0
IMSP0A 0xC41 Internal Memory DMA Access Modifier 0x0
CSP0A 0xC42 Contains Number of DMA Transfers Remaining 0x0
CPSP0A 0xC43 Points to Next DMA Parameters 0x0
IISP0B 0xC44 Internal Memory DMA Address 0x0
IMSP0B 0xC45 Internal Memory DMA Access Modifier 0x0
Register Mnemonic Address Description Reset
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