ADSP-214xx SHARC Processor Hardware Reference A-277
Registers Reference
CSP0B 0xC46 Contains Number of DMA Transfers Remaining 0x0
CPSP0B 0xC47 Points to Next DMA Parameters 0x0
IISP1A 0xC48 Internal Memory DMA Address 0x0
IMSP1A 0xC49 Internal Memory DMA Access Modifier 0x0
CSP1A 0xC4A Contains Number of DMA Transfers Remaining 0x0
CPSP1A 0xC4B Points to Next DMA Parameters 0x0
IISP1B 0xC4C Internal Memory DMA Address 0x0
IMSP1B 0xC4D Internal Memory DMA Access Modifier 0x0
CSP1B 0xC4E Contains Number of DMA Transfers Remaining 0x0
CPSP1B 0xC4F Points to Next DMA Parameters 0x0
TXSP0A 0xC60 SPORT 0A Transmit Data 0x0
RXSP0A 0xC61 SPORT 0A Receive Data 0x0
TXSP0B 0xC62 SPORT 0B Transmit Data 0x0
RXSP0B 0xC63 SPORT 0B Receive Data 0x0
TXSP1A 0xC64 SPORT 1A Transmit Data 0x0
RXSP1A 0xC65 SPORT 1A Receive Data 0x0
TXSP1B 0xC66 SPORT 1B Transmit Data 0x0
RXSP1B 0xC67 SPORT 1B Receive Data 0x0
Serial Port 2 and 3 Registers
SPCTL2 0x400 SPORT 2 Control 0x0000 0000
SPCTL3 0x401 SPORT 3 Control 0x0000 0000
SPCTLN2 0x41A SPORT 2 Control Register 2 0x0000 0000
SPCTLN3 0x41B SPORT 3 Control Register 2 0x0000 0000
DIV2 0x402 SPORT 2 Divisor for TX/RX SCLK2 and FS2 0x0
DIV3 0x403 SPORT 3 Divisor for TX/RX SCLK3 and FS3 0x0
SPMCTL2 0x404 SPORTs 2 TDM Control 0x0
MT2CS0 0x405 SPORT 2 TDM TX Select, CH31–0 0x0
Register Mnemonic Address Description Reset
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