ADSP-214xx SHARC Processor Hardware Reference A-275
Registers Reference
DDR2STAT1 0x1840 DDR2 Status 1 0x0
DDR2PADCTL0 0x1841 DDR2 Pad Control 0 0x200 0000
DDR2PADCTL1 0x1842 DDR2 Pad Control 1 0x8020
DLL0CTL1 0x1851 DLL0 Control Register 1 0x0
DLL0STAT0 0x1853 DLL0 Status Register 1 0x0
DLL1CTL1 0x1856 DLL1 Control Register 1 0x0
DLL1STAT0 0x1858 DLL1 Status Register 1 0x0
SDRAM Registers
SDCTL 0x1800 SDRAM Control 0x0102000A
SDRRC 0x1802 SDRAM Refresh Count 0x3081A
SDSTAT0 0x1803 SDRAM Status 0x8
SDSTAT1 0x1804 SDRAM Status 0x8
Global Serial Port Register
SPERRSTAT 0x2300 Global SPORT Error Status 0x0
Serial Port Error Control Registers
SPERRCTL0 0xC18 SPORT0 Error Control 0x0
SPERRCTL1 0xC19 SPORT1 Error Control 0x0
SPERRCTL2 0x418 SPORT2 Error Control 0x0
SPERRCTL3 0x419 SPORT3 Error Control 0x0
SPERRCTL4 0x818 SPORT4 Error Control 0x0
SPERRCTL5 0x819 SPORT5 Error Control 0x0
SPERRCTL6 0x4818 SPORT6 Error Control 0x0
SPERRCTL7 0x4819 SPORT7 Error Control 0x0
Serial Port 0 and 1 Registers
SPCTL0 0xC00 SPORT 0 Control Register 0x0000 0000
SPCTL1 0xC01 SPORT 1 Control Register 0x0000 0000
SPCTLN0 0xC1A SPORT 0 Control Register 2 0x0000 0000
Register Mnemonic Address Description Reset
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