ADSP-214xx SHARC Processor Hardware Reference A-281
Registers Reference
TXSP4A 0x860 SPORT 4A Transmit Data 0x0
RXSP4A 0x861 SPORT 4A Receive Data 0x0
TXSP4B 0x862 SPORT 4B Transmit Data 0x0
RXSP4B 0x863 SPORT 4B Receive Data 0x0
TXSP5A 0x864 SPORT 5A Transmit Data 0x0
RXSP5A 0x865 SPORT 5A Receive Data 0x0
TXSP5B 0x866 SPORT 5B Transmit Data 0x0
RXSP5B 0x867 SPORT 5B Receive Data 0x0
SPORT 6 and 7 Registers
SPCTL6 0x4800 SPORT 6 Control 0x0000 0000
SPCTL7 0x4801 SPORT 7 Control 0x0000 0000
SPCTLN6 0x481A SPORT 6 Control Register 2 0x0000 0000
SPCTLN7 0x481B SPORT 7 Control Register 2 0x0000 0000
DIV6 0x4802 SPORT 6 Divisor for TX/RX SCLK6 and FS6 0x0
DIV7 0x4803 SPORT 7 Divisor for TX/RX SCLK7 and FS7 0x0
SPMCTL6 0x4804 SPORT 6 TDM Control 0x0
MT6CS0 0x4805 SPORT 6 TDM TX Select, CH31–0 0x0
MT6CS1 0x4806 SPORT 6 TDM TX Select, CH63–32 0x0
MT6CS2 0x4807 SPORT 6 TDM TX Select, CH95–64 0x0
MT6CS3 0x4808 SPORT 6 TDM TX Select, CH127–96 0x0
MR7CS0 0x4809 SPORT 7 TDM RX Select, CH31–0 0x0
MR7CS1 0x480A SPORT 7 TDM RX Select, CH63–32 0x0
MR7CS2 0x480B SPORT 7 TDM RX Select, CH95–64 0x0
MR7CS3 0x480C SPORT 7 TDM RX Select, CH127–96 0x0
MT6CCS0 0x480D SPORT 6 TDM TX Compand Select, CH31–0 0x0
MT6CCS1 0x480E SPORT 6 TDM TX Compand Select, CH63–32 0x0
MT6CCS2 0x480F SPORT 6 TDM TX Compand Select, CH95–64 0x0
Register Mnemonic Address Description Reset
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