Register Listing
A-294 ADSP-214xx SHARC Processor Hardware Reference
DITCTL 0x24A0 Digital Interface Transmit Control 0x0
S/PDIF Channel Status Registers
DITCHANA0 0x24A1 Transmit CH0 Subframe A 0x0
DITCHANA1 0x24D4 Transmit CH1 Subframe A 0x0
DITCHANA2 0x24D5 Transmit CH2 Subframe A 0x0
DITCHANA3 0x24D6 Transmit CH3 Subframe A 0x0
DITCHANA4 0x24D7 Transmit CH4 Subframe A 0x0
DITCHANA5 0x24D8 Transmit CH5 Subframe A 0x0
DITCHANB0 0x24A2 Transmit CH0 Subframe B 0x0
DITCHANB1 0x24DA Transmit CH1 Subframe B 0x0
DITCHANB2 0x24DB Transmit CH2 Subframe B 0x0
DITCHANB3 0x24DC Transmit CH3 Subframe B 0x0
DITCHANB4 0x24DD Transmit CH4 Subframe B 0x0
DITCHANB5 0x24DE Transmit CH5 Subframe B 0x0
S/PDIF User Bit Status Registers
DITUSRBITA0 0x24E0 Transmit User Bit CH0 Subframe A 0x0
DITUSRBITA1 0x24E1 Transmit User Bit CH1 Subframe A 0x0
DITUSRBITA2 0x24E2 Transmit User Bit CH2 Subframe A 0x0
DITUSRBITA3 0x24E3 Transmit User Bit CH3 Subframe A 0x0
DITUSRBITA4 0x24E4 Transmit User Bit CH4 Subframe A 0x0
DITUSRBITA5 0x24E5 Transmit User Bit CH5 Subframe A 0x0
DITUSRBITB0 0x24E8 Transmit User Bit CH0 Subframe B 0x0
DITUSRBITB1 0x24E9 Transmit User Bit CH1 Subframe B 0x0
DITUSRBITB2 0x24EA Transmit User Bit CH2 Subframe B 0x0
DITUSRBITB3 0x24EB Transmit User Bit CH3 Subframe B 0x0
DITUSRBITB4 0x24EC Transmit User Bit CH4 Subframe B 0x0
Register Mnemonic Address Description Reset
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