ADSP-214xx SHARC Processor Hardware Reference A-295
Registers Reference
DITUSRBITB5 0x24ED Transmit User Bit CH5 Subframe B 0x0
DITUSRUPD 0x24EF Transmit User Bit Update 0x0
S/PDIF Receiver Registers
DIRCTL 0x24A8 Receiver Control 0x0
DIRSTAT 0x24A9 Receiver Status 0x20
DIRCHANL 0x24AA Receiver Left Channel Status 0x0
DIRCHANR 0x24AB Receiver Right Channel Status 0x0
Sample Rate Converter Registers
SRCCTL0 0x2490 SRC0 Control 0x0
SRCCTL1 0x2491 SRC1 Control 0x0
SRCMUTE 0x2492 SRC Mute 0x0
SRCRAT0 0x2498 SRC0 Output to Input Ratio 0x8000 8000
SRCRAT1 0x2499 SRC1 Output to Input Ratio 0x8000 8000
UART Registers
UART0LCR 0x3C03 UART0 Line Control 0x0
UART0LSR 0x3C05 UART0 Line Status 0x60
UART0THR 0x3C00 UART0 Transmit Hold 0x0
UART0RBR 0x3C00 UART0 Receive Buffer 0x0
UART0IER 0x3C01 UART0 Interrupt Enable 0x0
UART0IIR 0x3C02 UART0 Interrupt ID 0x1
UART0DLL 0x3C00 UART0 Divisor Latch Low 0x0
UART0DLH 0x3C01 UART0 Divisor Latch High 0x0
UART0SCR 0x3C07 UART0 Scratch Undefined
UART0MODE 0x3C04 UART0 Mode 0x20
RXI_UAC0 0x3E00 UART Receive Index Register 0x0
RXM_UAC0 0x3E01 UART Receive Modifier Register 0x0
RXC_UAC0 0x3E02 UART Receive Count Register 0x0
Register Mnemonic Address Description Reset
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