Register Listing
A-296 ADSP-214xx SHARC Processor Hardware Reference
RXCP_UAC0 0x3E03 UART Receive Chain Pointer Register 0x0
TXI_UAC0 0x3F00 UART Transmit Index Register 0x0
TXM_UAC0 0x3F01 UART Transmit Modifier Register 0x0
TXC_UAC0 0x3F02 UART Receive Count Register 0x0
TXCP_UAC0 0x3F03 UART Transmit Chain Pointer Register 0x0
UART0TXCTL 0x3F04 UART0 DMA TX Control 0x0
UART0RXCTL 0x3E04 UART0 DMA RX Control 0x0
UART0TXSTAT 0x3F05 UART0 DMA TX Status 0x0
UART0RXSTAT 0x3E05 UART0 DMA RX Status 0x0
TWI Registers
TWIDIV 0x4400 SCL Clock Divider 0x0
TWIMITR 0x4404 Master Internal Time Reference 0x0
TWISCTL 0x4408 Slave Mode Control 0x0
TWISSTAT 0x440C Slave Mode Status 0x0
TWISADDR 0x4410 Slave Mode Address 0x0
TWIMCTL 0x4414 Master Mode Control 0x0
TWIMSTAT 0x4418 Master Mode Status 0x0
TWIMADDR 0x441C Master Mode Address 0x0
TWIIRPTL 0x4420 Interrupt Latch 0x0
TWIIMASK 0x4424 Interrupt Mask 0x0
TWIFIFOCTL 0x4428 FIFO Control 0x0
TWIFIFOSTAT 0x442C FIFO Status 0x0
TXTWI 8 0x4480 8-bit FIFO Transmit 0x0
TXTWI 16 0x4484 16-bit FIFO Transmit 0x0
RXTWI8 0x4488 8-Bit FIFO Receive 0x0
RXTWI16 0x448C 16-Bit FIFO Receive 0x0
Register Mnemonic Address Description Reset
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