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ADSP-214xx SHARC Processor Hardware Reference 2-39

I/O Processor

17 D IDP_CTL,

IDP_CTL1,

IDP_CTL2,

IDP_PP_CTL,

DAI_STAT

IDP_DMA_I5,

IDP_DMA_M5,

IDP_DMA_C5,

IDP_DMA_I5A,

IDP_DMA_I5B,

IDP_DMA_PC5

IDP_FIFO Serial Input DAI

IDP Channel 5

18 IDP_DMA_I6,

IDP_DMA_M6,

IDP_DMA_C6,

IDP_DMA_I6A,

IDP_DMA_I6B,

IDP_DMA_PC6

Serial Input DAI

IDP Channel 6

19 IDP_DMA_I7,

IDP_DMA_M7,

IDP_DMA_C7,

IDP_DMA_I7A,

IDP_DMA_I7B,

IDP_DMA_PC7

Serial Input DAI

IDP Channel 7

20 E SPICTL,

SPIDMAC,

SPIBAUD

SPISTAT

IISPI, IMSPI,

CSPI, CPSPI

RXSPI or TXSPI

and DMA Buffer

SPI Data

21–51 F MLB_xCR Local SRAM Buf-

fer

MLB Data

52 G SPICTLB,

SPIDMACB,

SPIBAUDB,

SPISTATB

IISPIB, IMSPIB,

CSPIB, CPSPIB

RXSPIB or

TXSPIB and

DMA Buffer

SPI B Data

53 H MTMCTL (or

DTCP)

IIMTMW,

IMMTMW,

CMTMW

MTM FIFO Memory-to-

memory write data

54 I IIMTMR,

IMMTMR,

CMTMR

MTM FIFO Memory-to-

memory read data

Table 2-28. DMA Channel 0–66 Priorities (Cont’d)

DMA

Channel

Number

Peripheral

Group

Control/Status

Registers

Parameter

Registers

Data Buffer Description

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English

Analog Devices SHARC ADSP-214 Series User Manual

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Analog Devices SHARC ADSP-214 Series Specifications

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