Analog Devices SHARC ADSP-214 Series User Manual

Operating Modes
2-40 ADSP-214xx SHARC Processor Hardware Reference
55 J UART0RXCTL,
UART0RXSTAT
IIUART0RX,
IMUART0RX,
CUART0RX,
CPUART0RX,
UARTRBR0 Buf-
fer
UART0 Receive
Buffer Register
56 UART0TXCTL,
UART0TXSTAT
IIUART0TX,
IMUART0TX,
CUART0TX,
CPUART0TX,
UARTTHR0
Buffer
UART0 Transmit
Holding Register
57 K LCTL0,
LSTAT0
IILB0, IMLB0,
ICLB0, CPLB0
TXLB0
or
RXLB0
Link Port 0 Data
(ADSP-2146x
only)
58 LCTL1,
LSTAT1
IILB1, IMLB1,
ICLB1, CPLB1
TXLB0
or
RXLB0
Link Port 1 Data
(ADSP-2146x
only)
59 L SPCTL7,
SPMCTL7
IISP7A, IMSP7A,
CSP7A, CPSP7A
RXSP7A
or
TXSP7A
Serial Port 7A Data
60 IISP7B, IMSP7B,
CSP7B, CPSP7B
RXSP7B
or
TXSP7B
Serial Port 7B Data
61 SPCTL6,
SPMCTL6
IISP6A, IMSP6A,
CSP6A, CPSP6A
RXSP6A
or
TXSP6A
Serial Port 6A Data
62 IISP6B, IMSP6B,
CSP6B, CPSP6B
RXSP6B
or
TXSP6B
Serial Port 6B Data
Table 2-28. DMA Channel 0–66 Priorities (Cont’d)
DMA
Channel
Number
Peripheral
Group
Control/Status
Registers
Parameter
Registers
Data Buffer Description
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Analog Devices SHARC ADSP-214 Series Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English