Analog Devices SHARC ADSP-214 Series

Operating Modes
2-38 ADSP-214xx SHARC Processor Hardware Reference
12 D IDP_CTL,
IDP_CTL1,
IDP_CTL2,
IDP_PP_CTL,
DAI_STAT
IDP_DMA_I0,
IDP_DMA_M0,
IDP_DMA_C0,
IDP_DMA_I0A,
IDP_DMA_I0B,
IDP_DMA_PC0
IDP_FIFO DAI IDP or
PDAP
(only channel 0
supports both
13 IDP_DMA_I1,
IDP_DMA_M1,
IDP_DMA_C1,
IDP_DMA_I1A,
IDP_DMA_I1B,
IDP_DMA_PC1
Serial Input DAI
IDP
Channel 1
14 IDP_DMA_I2,
IDP_DMA_M2,
IDP_DMA_C2,
IDP_DMA_I2A,
IDP_DMA_I2B,
IDP_DMA_PC2
Serial Input DAI
IDP Channel 2
15 IDP_DMA_I3,
IDP_DMA_M3,
IDP_DMA_C3,
IDP_DMA_I3A,
IDP_DMA_I3B,
IDP_DMA_PC3
Serial Input DAI
IDP Channel 3
16 IDP_DMA_I4,
IDP_DMA_M4,
IDP_DMA_C4,
IDP_DMA_I4A,
IDP_DMA_I4B,
IDP_DMA_PC4
Serial Input DAI
IDP Channel 4
Table 2-28. DMA Channel 0–66 Priorities (Cont’d)
DMA
Channel
Number
Peripheral
Group
Control/Status
Registers
Parameter
Registers
Data Buffer Description
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