ADSP-214xx SHARC Processor Hardware Reference 18-13
Real-Time Clock—ADSP-2147x
To ensure that writes between the core voltage and RTC voltage
domain are properly synchronized, all write commands should be
issued immediately after a seconds’ event in the RTC_STAT register.
This two step sequence results in a write latency of up to 1 second. While
the write sequence is ongoing, the write pending (WR_PEND) bit is set in the
RTC_STAT register and is cleared by hardware when the process is complete.
Resetting or powering down the peripherals while a write is in progress,
(that is when this bit is set) is forbidden. Subsequent writes to the same
register before completion of the previous write are ignored.
Do not attempt write to the RTC_CLOCK, RTC_ALARM or RTC_SWTCH
registers when the RTC oscillator is powered down or when the
RTC_READEN bit is set.
During initialization, after a write of the RTC_INIT register, make
sure that the WR_PEND bit is cleared before attempting writes to
other registers.
Power-Up, Power-Down and Reset
The inclusion of the power-down bit (RTCPDN) as well as the possibility
that the RTC may not be used in certain applications introduces specific
constraints on the power-up and reset behavior of the RTC. These are
described below.
1. When the RTC is powered-up for the first time, it remains in an
undefined state until the core powers-up and the corresponding
power-down bit in the RTC_INIT register is written by software.
Programs should clear
RTCPDN if the RTC function is desired and
set if it is not.
2. After clearing the
RTCPDN bit the application has to wait at least
until the first seconds’ event before it writes the timer and alarm
registers. This is because the oscillator takes a TSTARTUP time
before the clock gets generated.
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