Interrupts
18-16 ADSP-214xx SHARC Processor Hardware Reference
Writes posted together at the beginning of the same second take effect
together at the next 1 Hz tick. The following sequence is safe and does not
result in any spurious interrupts from a previous state.
1. Wait for 1 Hz tick.
2. Write new values for
RTC_CLOCK, RTC_ALARM, and/or RTC_SWCNT.
3. Write 1s to clear the RTC_CLOCK flags for Alarm, Day Alarm, Stop-
watch, and/or per-interval.
4. Write new value for RTC_CTL with Alarm, Day Alarm, Stopwatch,
and/or per-interval interrupts enabled.
5. Wait for 1 Hz tick.
6. New values have now taken effect simultaneously.
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