ADSP-214xx SHARC Processor Hardware Reference 19-5
WatchDog Timer – ADSP-2147x
it counts to zero from the programmed value. This protects the system
from remaining in an unknown state where software, which would nor-
mally reload the timer, has stopped running due to an external event or
software error. When used in this way, software reloads the watchdog
timer in a regular manner so that the downward counting timer never
expires. An expiring timer then indicates that system software might be
out of control.
The watchdog timer resets both the core and the internal peripherals.
After an external reset, the WDT must be disabled by default. Software
must be able to determine if the watchdog was the source of the hardware
reset by interrogating a status bit in the watchdog timer control register.
As shown in Figure 19-1 the clock source for the watchdog timer can be
selected from either the internal RC oscillator or from an external
oscillator.
The expired timer performs a software reset (reset core and the
peripherals). For more information, see “Processor Reset” on
page 23-3.
After an external reset, the WDT must be disabled by default. Software
must be able to determine if the watchdog was the source of the hardware
reset by interrogating a status bit in the watchdog timer control register.
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