ADSP-214xx SHARC Processor Hardware Reference 23-5
System Design
• The processor core and peripherals are reset exactly as if a
Power-on (hardware) reset is asserted, except:
• The SDRAM/DDR2 controllers continue to run and
refresh as programmed.
• The contents of external SDRAM/DDR2 are unaffected,
and retain their values prior to a running reset.
• A system boot is NOT initiated. Instead, the program coun-
ter is cleared and program execution begins from the very
first location of program memory (from the reset interrupt
vector table).
Running reset allows programs to:
• Execute self-modifying code that has previously overwritten exist-
ing code in internal memory.
• Activate an external watchdog in cases where there is a malfunction
or exception within a peripheral.
• Perform a context reset of the processor sufficient to restore the
state, (in cases where a complete boot is not required).
The RUNRSTCTL register is reset only on assertion of a hardware
reset, software reset, emulator reset, or by writing to the appropri-
ate bits of the RUNRSTCTL register via software.
For emulation reset, see the SHARC Processor Programming Reference,
“JTAG” chapter.
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