Peripheral Registers
A-70 ADSP-214xx SHARC Processor Hardware Reference
Table A-37. PWMCTLx Register Bit Descriptions (RW)
Bit Name Description
0 PWM_ALIGN Align Mode.
0 = Edge-aligned. The PWM waveform is left-justified in the period
window.
1 = Center-aligned. The PWM waveform is symmetrical.
1 PWM_PAIR Pair Mode.
0 = Non-paired mode. The PWM generates independent signals (for
example xH, xL)
1 = Paired mode. The PWM generates the complementary signal
from the high side output (xL=/xH).
2 PWM_UPDATE Update Mode.
0 = Single update mode. The duty cycle values are programmable
only once per PWM period. The resulting PWM patterns are sym-
metrical about the mid-point of the PWM period.
1 = Double update mode. A second update of the PWM registers is
implemented at the mid-point of the PWM period. PWM_UPDATE
mode has only effect for center aligned mode (PWM_ALIGN=1).
4–3 Reserved
5 PWM_IRQEN Enable PWM Interrupts.
0 = Interrupts not enabled
1 = Interrupts enabled
15–6 Reserved
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