ADSP-214xx SHARC Processor Hardware Reference A-221
Registers Reference
Figure A-122. SRU2_INPUT4 Register (RW)
Figure A-123. SRU2_INPUT5 Register (RW)
Table A-118. Group A Connections
Selection Code Signal Description (Source Selection)
00000 (0x0) LOW Logic Level Low (0)
00001 (0x1) HIGH Logic Level High (1)
00010 (0x2) DPI_PB01_O External Pin 1
00011 (0x3) DPI_PB02_O External Pin 2
Miscellaneous B0 Input
FLAG15_I (14–10)
Flag 15 Input
FLAG14_I (9–5)
Flag 14 Input
FLAG13_I (4–0)
Flag 13 Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
MISCB0_I (19–15)
MISCB0_I (19–15)
Miscellaneous B1 Input
MISCB1_I (24–20)
Miscellaneous B2 Input
MISCB2_I (29–25)
Miscellaneous B6 Input
MISCB5_I (14–10)
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
MISCB6_I (19–15)
MISCB6_I (19–15)
Miscellaneous B7 Input
MISCB7_I (24–20)
Miscellaneous B8 Input
MISCB8_I (29–25)
Miscellaneous B3 Input
MISCB3_I (4–0)
Miscellaneous B4 Input
MISCB4_I (9–5)
Miscellaneous B5 Input
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