DPI Signal Routing Unit Registers
A-220 ADSP-214xx SHARC Processor Hardware Reference
Figure A-120. SRU2_INPUT2 Register (RW)
Figure A-121. SRU2_INPUT3 Register (RW)
FLAG6_I (29–25)
Flag 6 Input
FLAG4_I (19–15) con’t
Flag 4 Input
FLAG5_I (24–20)
Flag 5 Input
TIMER1_I (9–5)
Timer 1 Input
TIMER0_I (4–0)
Timer 0 Input
FLAG4_I (14–10)
Flag 4 Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
FLAG12_I (29–25)
Flag 12 Input
FLAG10_I (19–15) con’t
Flag 10 Input
FLAG11_I (24–20)
Flag 11 Input
FLAG9_I (14–10)
Flag 9 Input
FLAG8_I (9–5)
Flag 8 Input
FLAG7_I (4–0)
Flag 7 Input
FLAG10_I (19–15)
Flag 10 Input
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315