Analog Devices SHARC ADSP-214 Series - Page 23

ADSP-214xx SHARC Processor Hardware Reference xxiii
Contents
Duty Cycles ........................................................................ 7-7
Dead Time ....................................................................... 7-12
Output Control Unit ............................................................. 7-13
Output Enable .................................................................. 7-13
Output Polarity ................................................................. 7-13
Complementary Outputs .................................................. 7-14
Crossover .......................................................................... 7-14
Emergency Dead Time for Over Modulation .......................... 7-15
Output Control Feature Precedence ................................... 7-17
Operation Modes ........................................................................ 7-18
Waveform Modes .................................................................. 7-18
Edge-Aligned Mode .......................................................... 7-18
Center-Aligned Mode ........................................................ 7-19
PWM Timer Edge Aligned Update ........................................ 7-21
Single Update Mode .......................................................... 7-22
Double Update Mode ....................................................... 7-22
Effective Accuracy ................................................................. 7-23
Synchronization of PWM Groups ......................................... 7-24
Interrupts ................................................................................... 7-25
Debug Features ........................................................................... 7-27
Status Debug Register ............................................................ 7-27
Emulation Considerations ..................................................... 7-27
Effect Latency ............................................................................. 7-27
Write Effect Latency .............................................................. 7-27
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