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Analog Devices SHARC ADSP-214 Series - Page 24

Analog Devices SHARC ADSP-214 Series
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Contents
xxiv ADSP-214xx SHARC Processor Hardware Reference
PWM Effect Latency ............................................................. 7-27
MEDIA LOCAL BUS
Features ........................................................................................ 8-3
Pin Descriptions ........................................................................... 8-3
Register Overview ......................................................................... 8-4
Device Configuration and Status Registers ............................... 8-4
Channel Configuration Registers ............................................. 8-4
Clocking ...................................................................................... 8-5
Functional Description ................................................................. 8-5
Operating Modes .......................................................................... 8-7
Streaming Channel Frame Synchronization .............................. 8-7
Big-Endian and Little-Endian Mode ....................................... 8-8
Data Transfer ............................................................................... 8-8
Core Driven Data Transfer ...................................................... 8-8
I/O Local Channel Buffering .............................................. 8-8
DMA .................................................................................... 8-10
Ping-Pong DMA ............................................................... 8-11
Circular Buffer DMA ....................................................... 8-13
Interrupts ................................................................................... 8-14
Interrupt Source .................................................................... 8-15
Servicing Interrupts ............................................................... 8-15
Debug Features ........................................................................... 8-15
Loop-Back Test Mode ........................................................... 8-16
Programming Model ................................................................... 8-16
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