Analog Devices SHARC ADSP-214 Series - Page 27

ADSP-214xx SHARC Processor Hardware Reference xxvii
Contents
Effect Latency ............................................................................. 9-42
Write Effect Latency .............................................................. 9-42
Signal Routing Unit Effect Latency ........................................ 9-42
Programming Model ................................................................... 9-42
DAI Example System ............................................................. 9-43
SERIAL PORTS
Features ...................................................................................... 10-2
Pin Descriptions ......................................................................... 10-4
SRU Programming ...................................................................... 10-5
SRU SPORT Receive Master ................................................. 10-6
SRU SPORT Signal Integrity ................................................. 10-6
Register Overview ....................................................................... 10-7
Clocking ..................................................................................... 10-8
Master Clock ......................................................................... 10-8
Master Frame Sync ................................................................ 10-9
Slave Mode .......................................................................... 10-10
Functional Description ............................................................. 10-10
Architecture ........................................................................ 10-11
Data Types and Companding ............................................... 10-12
Companding the Data Stream ......................................... 10-13
Transmit Path ................................................................. 10-14
Receive Path ................................................................... 10-15
Frame Sync ......................................................................... 10-16
Sampling Edge ................................................................ 10-16
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