Contents
xxviii ADSP-214xx SHARC Processor Hardware Reference
Frame Sync and Data Sampling ....................................... 10-16
Serial Word Length ......................................................... 10-18
Internal Versus External Frame Syncs ............................. 10-18
External Frame Sync Sampling .................................... 10-19
Logic Level Frame Syncs ............................................. 10-20
Data-Independent Frame Sync ................................... 10-20
Operation Modes ..................................................................... 10-21
Mode Selection ................................................................... 10-23
Channel Order First ....................................................... 10-24
Standard Serial Mode .......................................................... 10-25
Timing Control Bits ....................................................... 10-25
Clocking Options .......................................................... 10-26
Frame Sync Options ....................................................... 10-26
Framed Versus Unframed Frame Syncs ............................ 10-26
Early Versus Late Frame Syncs ........................................ 10-27
Left-Justified Mode ............................................................. 10-28
Master Serial Clock and Frame Sync Rates ...................... 10-29
Timing Control Bits ....................................................... 10-29
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2
S Mode ............................................................................ 10-30
Master Serial Clock and Frame Sync Rates ...................... 10-30
Timing Control Bits ....................................................... 10-30
Multichannel Mode ............................................................ 10-31
Clocking Options ........................................................... 10-32
Frame Sync Options ....................................................... 10-32
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