Analog Devices SHARC ADSP-214 Series - Page 50

Contents
l ADSP-214xx SHARC Processor Hardware Reference
DDR2 Control Register 5 (DDR2CTL5) ......................... A-35
Refresh Rate Control Register (DDR2RRC) ...................... A-36
Controller Status Register 0 (DDR2STAT0) ...................... A-37
Controller Status Register 1 (DDR2STAT1) ..................... A-39
DLL0 Control Register 1 (DLL0CTL1) ........................... A-40
DLL1 Control Register 1 (DLL1CTL1) ........................... A-41
DLL Status Registers (DLL0STAT0, DLL1STAT0) ........... A-42
DDR2 Pad Control Register 0 (DDR2PADCTL0) ........... A-43
DDR2 Pad Control Register 1 (DDR2PADCTL1) ........... A-44
ADSP-2147x, ADSP-2148x External Port Registers ..................... A-45
External Port Control Register (EPCTL) ............................... A-45
AMI Control Registers (AMICTLx) ...................................... A-47
AMI Status Register (AMISTAT) ........................................... A-51
SDRAM Registers ................................................................. A-51
Control Register (SDCTL) ............................................... A-51
Control Status Register 0 (SDSTAT0) ............................... A-55
Controller Status Register 1 (SDSTAT1) .......................... A-57
Refresh Rate Control Register (SDRRC) ........................... A-58
External Port DMA Control Registers (DMACx) ......................... A-60
Peripheral Registers ..................................................................... A-63
Link Port Registers ................................................................ A-63
Control Register (LCTLx) ................................................ A-63
Status Registers (LSTATx) ................................................. A-65
Memory-to-Memory Registers ............................................... A-66
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