ADSP-214xx SHARC Processor Hardware Reference li
Contents
DMA Control (MTMCTL Register) ................................ A-66
Pulse Width Modulation Registers ........................................ A-67
Global Control Register (PWMGCTL) ............................ A-67
Global Status Register (PWMGSTAT) .............................. A-69
Control Register (PWMCTLx) ......................................... A-69
Status Registers (PWMSTATx) ......................................... A-71
Output Disable Registers (PWMSEGx) ............................ A-71
Polarity Select Registers (PWMPOLx) .............................. A-72
Period Registers (PWMPERIODx) ................................... A-73
Duty Cycle High Side Registers (PWMAx, PWMBx) ........ A-73
Duty Cycle Low Side Registers (PWMALx, PWMBLx) ..... A-74
Dead Time Registers (PWMDTx) .................................... A-74
Debug Status Registers (PWMDBGx) .............................. A-74
FFT Accelerator Registers ..................................................... A-74
General Control Register (FFTCTL1) .............................. A-75
Control Register (FFTCTL2) ........................................... A-76
Multiplier Status Register (FFTMACSTAT) ...................... A-78
DMA Status Register ........................................................ A-78
Debug Registers (FFTDADDR, FFTDDATA) .................. A-79
FIR Accelerator Registers ...................................................... A-79
Global Control Register (FIRCTL1) ................................. A-79
Channel Control Register (FIRCTL2) .............................. A-81
FIR MAC Status Register (FIRMACSTAT) ...................... A-83
FIR DMA Status Register (FIRDMASTAT) ...................... A-85
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