Analog Devices SHARC ADSP-214 Series - Page 52

Contents
lii ADSP-214xx SHARC Processor Hardware Reference
FIR Debug Registers (FIRDEBUGCTL,
FIRDBGADDR) ........................................................... A-86
IIR Accelerator Registers ....................................................... A-87
IIR Global Control Register (IIRCTL1) ............................ A-87
IIR Channel Control Register (IIRCTL2) ......................... A-90
IIR MAC Status Register (IIRMACSTAT) ........................ A-91
IIR DMA Status Register (IIRDMASTAT) ........................ A-91
IIR Debug Registers (IIRDEBUGCTL,
IIRDEBUGADDR) ....................................................... A-93
Media Local Bus Registers ..................................................... A-94
MLB Global Registers ....................................................... A-94
Device Control Configuration Register (MLB_DCCR) . A-94
System Status Register (MLB_SSCR) ............................ A-96
System Data Configuration Register (MLB_SDCR) .... A-97
System Mask Configuration Register (MLB_SMCR) ..... A-98
Channel Interrupt Status Register (MLB_CICR) ........... A-99
MLB Base Registers ...................................................... A-99
Logical Channel Registers ............................................... A-101
Channel Control Registers (MLB_CECRx) ................. A-102
Channel Status Configuration Registers
(MLB_CSCRx) ........................................................ A-108
Channel x Current Buffer Configuration Registers
(MLB_CCBCRx) .................................................. A-111
Channel x Next Buffer Configuration Registers
(MLB_CNBCRx) .................................................... A-112
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