ADSP-214xx SHARC Processor Hardware Reference liii
Contents
Local Buffer Configuration Registers
(MLB_LCBCRx) ..................................................... A-112
Watchdog Timer Registers .................................................. A-114
Control (WDTCTL) ...................................................... A-114
Status (WDTSTATUS) .................................................. A-114
Current Count (WDTCURCNT) .................................. A-115
Trip Counter (WDTTRIP) ............................................ A-115
Clock Select (WDTCLKSEL) ......................................... A-116
Period (WDTCNT) ....................................................... A-117
Unlock (WDTUNLOCK) .............................................. A-117
DAI Signal Routing Unit Registers ........................................... A-118
Clock Routing Control Registers
(SRU_CLKx, Group A) .................................................. A-118
Serial Data Routing Registers (SRU_DATx, Group B) ......... A-123
Frame Sync Routing Control Registers
(SRU_FSx, Group C) ..................................................... A-128
Pin Signal Assignment Registers
(SRU_PINx, Group D) .................................................... A-132
Miscellaneous Signal Routing Registers
(SRU_MISCx, Group E) ................................................. A-138
DAI Pin Buffer Enable Registers
(SRU_PBENx, Group F) ................................................. A-141
DAI Shift Register Routing Registers
(Group G, ADSP-2147x) ................................................. A-145
Clock Routing Register (SRU_CLK_SHREG) ................ A-145
Data Routing Register (SRU_DAT_SHREG) ................. A-147
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