Analog Devices SHARC ADSP-214 Series - Page 54

Contents
liv ADSP-214xx SHARC Processor Hardware Reference
DAI Pin Buffer Registers ..................................................... A-148
Pin Buffer Registers (DAI_PIN_STAT) ........................... A-148
Interrupt Controller Registers .............................................. A-149
Peripherals Routed Through the DAI ........................................ A-150
Serial Port Registers ............................................................. A-150
SPORT Divisor Registers (DIVx) .................................... A-151
Serial Control Registers (SPCTLx) .................................. A-151
SPORT Control 2 Registers (SPCTLNx) ......................... A-167
SPORT Multichannel Control Registers (SPMCTLx) ..... A-169
SPORT Active Channel Select Registers (MTxCSy
or MRxCSy) ................................................................ A-171
SPORT Compand Registers (MTxCCSy or MRxCCSy) .. A-172
Error Control Register (SPERRCTLx) ............................. A-172
SPORT Error Status Register (SPERRSTAT) ................... A-174
Input Data Port Registers .................................................... A-174
Input Data Port DMA Control Registers ......................... A-174
Input Data Port Control Register 0 (IDP_CTL0) ............ A-175
Input Data Port Control Register 1 (IDP_CTL1) ............ A-177
Input Data Port Control Register 2 (IDP_CTL2) ............ A-178
Parallel Data Acquisition Port Control Register
(IDP_PP_CTL) ........................................................... A-179
IDP Status Register (DAI_STAT0) .................................. A-182
IDP Status Register 1 (DAI_STAT1) ............................... A-183
Sample Rate Converter Registers ......................................... A-184
Control Registers (SRCCTLx) ........................................ A-184
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