Analog Devices SHARC ADSP-214 Series - Page 55

ADSP-214xx SHARC Processor Hardware Reference lv
Contents
Mute Register (SRCMUTE) ........................................... A-189
Ratio Registers (SRCRATx) ............................................ A-189
Precision Clock Generator Registers .................................... A-191
Control Registers (PCG_CTLxy) ................................... A-191
Clock Inputs .................................................................. A-193
Pulse Width Registers (PCG_PWx) ................................ A-194
PCG Frame Synchronization Registers (PCG_SYNCx) ... A-196
Sony/Philips Digital Interface Registers ............................... A-199
Transmitter Registers ...................................................... A-199
Transmit Control Register (DITCTL) ......................... A-199
Transmit Status Bit Registers for Subframe A/B
(DITCHANAx/Bx) ................................................. A-202
Transmit User Bits Buffer Registers for Subframe A/B
Registers (DITUSRBITAx/Bx) ................................. A-203
User Bit Update Register (DITUSRUPD) ................... A-204
Receiver Registers ........................................................... A-204
Receive Control Register (DIRCTL) ........................... A-204
Receive Status Register (DIRSTAT) ............................ A-206
Receive Status Registers for Subframe A
(DIRCHANA) ........................................................ A-209
Receive Status Registers for Subframe B
(DIRCHANB) ........................................................ A-209
Real-Time Clock Registers .................................................. A-209
Control Register (RTC_CTL) ........................................ A-210
Status Register (RTC_STAT) .......................................... A-211
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