ADSP-214xx SHARC Processor Hardware Reference lvii
Contents
UART Control and Status Registers .................................... A-243
Line Control Register (UART0LCR) .............................. A-243
Line Status Register (UART0LSR) .................................. A-245
Interrupt Enable Register (UART0IER) .......................... A-246
Interrupt Identification Registers (UART0IIR,
UART0IIRSH) ........................................................... A-247
Divisor Latch Registers (UART0DLL, UART0DLH) ...... A-249
Scratch Register (UART0SCR) ....................................... A-249
Mode Register (UART0MODE) ..................................... A-249
Buffer Control Registers (UART0TXCTL,
UART0RXCTL) ......................................................... A-251
DMA Status Registers (UART0TXSTAT,
UART0RXSTAT) ........................................................ A-252
Two Wire Interface Registers .............................................. A-253
Master Internal Time Register (TWIMITR) ................... A-253
Clock Divider Register (TWIDIV) ................................. A-254
Slave Mode Control Register (TWISCTL) ..................... A-255
Slave Address Register (TWISADDR) ............................ A-256
Slave Status Register (TWISSTAT) ................................. A-256
Master Control Register (TWIMCTL) ........................... A-257
Master Address Register (TWIMADDR) ........................ A-260
Master Status Register (TWIMSTAT) ............................. A-260
FIFO Control Register (TWIFIFOCTL) ........................ A-263
FIFO Status Register (TWIFIFOSTAT) ......................... A-264
Interrupt Latch Register (TWIIRPTL) ............................ A-265
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