Contents
lviii ADSP-214xx SHARC Processor Hardware Reference
Interrupt Enable Register (TWIIMASK) ......................... A-267
Peripheral Timer Registers ................................................... A-269
Read-Modify-Write Timer Control Register .................... A-269
Timer Configuration Registers (TMxCTL) ...................... A-270
Timer Status Registers (TMxSTAT) ................................ A-271
Register Listing ......................................................................... A-273
PERIPHERAL INTERRUPT CONTROL
Interrupt Latency ......................................................................... B-1
Interrupt Acknowledge ................................................................. B-2
Interrupt Completion ................................................................... B-3
Interrupt Priority .......................................................................... B-4
Peripherals with Multiple Interrupt Vector Addresses ............... B-7
Priority Interrupt Control Registers (PICRx) ........................... B-8
AUDIO FRAME FORMATS
Overview ...................................................................................... C-2
Standard Serial Mode .................................................................... C-2
I
2
S Mode ..................................................................................... C-3
Left-Justified Mode ....................................................................... C-5
Right-Justified Mode .................................................................... C-5
TDM Mode ................................................................................. C-6
Packed I
2
S Mode .................................................................... C-7
MOST Mode .......................................................................... C-8
AES/EBU/SPDIF Formats ............................................................ C-9
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