Manual Contents
lxiv ADSP-214xx SHARC Processor Hardware Reference
• Chapter 15, “Serial Peripheral Interface Ports”
Describes the operation of the serial peripheral interface (SPI) port.
SPI devices communicate using a master-slave relationship and can
achieve high data transfer rate because they can operate in
full-duplex mode.
• Chapter 16, “Peripheral Timers”
Describes three identical 32-bit timers that can be used to interface
with external devices.
• Chapter 17, “Shift Register – ADSP-2147x”
Describes the 18 stage serial in, serial/parallel out shift register.
• Chapter 18, “Real-Time Clock—ADSP-2147x”
Describes the digital watch features.
• Chapter 19, “WatchDog Timer – ADSP-2147x”
Describes software watchdog function which can improve system
reliability by forcing the processor to a known state.
• Chapter 20, “UART Port Controller”
Describes the operation of the Universal Asynchronous
Receiver/Transmitter (UART) which is a full-duplex peripheral
compatible with PC-style industry-standard UART.
• Chapter 21, “Two Wire Interface Controller”
The two wire interface is fully compatible with the widely used I
2
C
bus standard. It is designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations.
• Chapter 22, “System Design”
Describes system design features of the ADSP-214xx processors.
These include power, reset, clock, JTAG, and booting, as well as
pin multiplexing schemes and other system-level information.
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