Contents
viii ADSP-214xx SHARC Processor Hardware Reference
Data Packing .................................................................... 3-15
External Access Extension ................................................ 3-15
Predictive Reads ............................................................... 3-16
SDRAM Controller
(ADSP-2147x/ADSP-2148x) ................................................... 3-17
Features ................................................................................ 3-17
Functional Description ......................................................... 3-18
SDRAM Commands ........................................................ 3-20
Load Mode Register ...................................................... 3-20
Bank Activation ............................................................ 3-21
Single Precharge ........................................................... 3-21
Precharge All ................................................................ 3-22
Read/Write ................................................................... 3-22
Auto-Refresh ................................................................ 3-24
No Operation/Command Inhibit .................................. 3-24
Command Truth Table ................................................. 3-24
Address Mapping .............................................................. 3-25
Address Translation Options ......................................... 3-26
Address Width Settings ................................................. 3-27
16-Bit Address Mapping ................................................... 3-28
Refresh Rate Control ........................................................ 3-32
Internal SDRAM Bank Access ........................................... 3-34
Single Bank Access ........................................................ 3-34
Multibank Access .......................................................... 3-35
Multi Bank Operation with Data Packing ..................... 3-36
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