ADSP-214xx SHARC Processor Hardware Reference ix
Contents
Timing Parameters ............................................................ 3-37
Fixed Timing Parameters ............................................... 3-37
Data Mask ........................................................................ 3-38
Resetting the Controller .................................................... 3-38
Operating Modes ................................................................... 3-38
Parallel Connection of SDRAMs ....................................... 3-38
Buffering Controller for Multiple SDRAMs ................... 3-39
SDRAM Read Optimization ............................................. 3-40
Core Accesses ................................................................ 3-41
DMA Access ................................................................. 3-43
Notes on Read Optimization ......................................... 3-43
Self-Refresh Mode ............................................................. 3-44
Forcing SDRAM Commands ............................................. 3-45
Force Precharge All ....................................................... 3-45
Force Load Mode Register ............................................. 3-46
Force Auto-Refresh ........................................................ 3-46
DDR2 DRAM Controller (ADSP-2146x) .................................... 3-46
Features ................................................................................. 3-46
Pin Descriptions .................................................................... 3-48
Functional Description .......................................................... 3-48
DDR2 Commands ............................................................ 3-51
Load Mode Register ...................................................... 3-51
Load Extended Mode Register ...................................... 3-52
Load Extended Mode Register 2 ................................... 3-53
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