External Port DMA Control Registers (DMACx)
A-62 ADSP-214xx SHARC Processor Hardware Reference
9TLENScatter/Gather (Tap List) DMA Enable.
0 = Disables the tap list based scatter/gather DMA
1 = Enables the tap list based scatter/gather DMA
11–10 Reserved
12 INTIRT Internal DMA Completion Interrupt (Control).
0 = Interrupt on access completion (internal/external DMA com-
pletion depending on external read/write)
1 = Interrupt on internal DMA completion
This bit is provided for backward compatibility with older
SHARC processors.
15–13 Reserved
17–16 (RO) DFS DMA FIFO Status.
00 = FIFO Empty
01 = FIFO Partially Full
11 = FIFO Full
10 = Reserved
19–18 Reserved
20 (RO) DMAS DMA Transfer Status.
0 = DMA idle
1 = DMA in progress
21 (RO) CHS DMA Chaining Status.
0 = DMA chain loading is not active
1 = DMA chain loading is active
22 (RO) TLS TAP List Loading Status.
1 = TAP list loading is active
0 = TAP list loading is not active
23 (RO) WBS Delay Line Write Pointer Write Back Status.
0 = Write pointer write back is not active
1 = Write pointer write back is active
24 (RO) EXTS DMA External Interface Status.
0 = DMA external interface does not have any access pending
1 = DMA external interface has access pending
Table A-32. External Port DMA Register Bit Descriptions (RW) (Cont’d)
Bit Name Description
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