ADSP-214xx SHARC Processor Hardware Reference A-137
Registers Reference
1000011 (0x43) DIR_CLK_O SPDIF_RX Clock Output
1000100 (0x44) DIR_TDMCLK_O SPDIF_RX TDM Clock Output
1000101 (0x45) DIT_O SPDIF TX Biphase Encoded Data Output
1000110 (0x46) SPORT0_TDV_O SPORT0 Transmit Data Valid Output
1000111 (0x47) SPORT1_TDV_O SPORT1 Transmit Data Valid Output
1001000 (0x48) SPORT2_TDV_O SPORT2 Transmit Data Valid Output
1001001 (0x49) SPORT3_TDV_O SPORT3 Transmit Data Valid Output
1001010 (0x4A) SPORT4_TDV_O SPORT4 Transmit Data Valid Output
1001011 (0x4B) SPORT5_TDV_O SPORT5 Transmit Data Valid Output
1001100 (0x4C) SPORT6_TDV_O SPORT6 Transmit Data Valid Output
1001101 (0x4D) SPORT7_TDV_O SPORT7 Transmit Data Valid Output
1001110 (0x4E) DIR_LRCLK_REF_O External PLL – Reference Point
Connection
1001111 (0x4F) DIR_LRCLK_FB_O External PLL – Feedback Point Connection
1010000 (0x50) PCG_CLKC_O Precision Clock C
1011001 (0x51) PCG_CLKD_O Precision Clock D
1011010 (0x52) PCG_FSC_O Precision Frame Sync C
1010011 (0x53) PCG_FSD_O Precision Frame Sync D
1010100 – 1111101 Reserved
1111110 (0x7E) LOW Logic Level Low (0)
1111111 (0x7F) HIGH Logic Level High (1)
Table A-78. Group D Sources – Pin Signal Assignments (Cont’d)
Selection Code Source Signal Description (Source Selection)
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