ADSP-214xx SHARC Processor Hardware Reference A-143
Registers Reference
Table A-80. Group F Sources – Pin Output Enable
Selection Code Source Signal Description (Output Source Selection)
000000 (0x0) LOW Logic Level Low (0)
000001 (0x1) HIGH Logic Level High (1)
000010 (0x2) MISCA0_O Miscellaneous Control A0 Output
000011 (0x3) MISCA1_O Miscellaneous Control A1 Output
000100 (0x4) MISCA2_O Miscellaneous Control A2 Output
000101 (0x5) MISCA3_O Miscellaneous Control A3 Output
000110 (0x6) MISCA4_O Miscellaneous Control A4 Output
000111 (0x7) MISCA5_O Miscellaneous Control A5 Output
001000 (0x8) SPORT0_CLK_PBEN_O SPORT 0 Clock Output Enable
001001 (0x9) SPORT0_FS_PBEN_O SPORT 0 Frame Sync Output Enable
001010 (0xA) SPORT0_DA_PBEN_O SPORT 0 Data Channel A Output Enable
001011 (0xB) SPORT0_DB_PBEN_O SPORT 0 Data Channel B Output Enable
001100 (0xC) SPORT1_CLK_PBEN_O SPORT 1 Clock Output Enable
001101 (0xD) SPORT1_FS_PBEN_O SPORT 1 Frame Sync Output Enable
001110 (0xE) SPORT1_DA_PBEN_O SPORT 1 Data Channel A Output Enable
001111 (0xF) SPORT1_DB_PBEN_O SPORT 1 Data Channel B Output Enable
010000 (0x10) SPORT2_CLK_PBEN_O SPORT 2 Clock Output Enable
010001 (0x11) SPORT2_FS_PBEN_O SPORT 2 Frame Sync Output Enable
010010 (0x12) SPORT2_DA_PBEN_O SPORT 2 Data Channel A Output Enable
010011 (0x13) SPORT2_DB_PBEN_O SPORT 2 Data Channel B Output Enable
010100 (0x14) SPORT3_CLK_PBEN_O SPORT 3 Clock Output Enable
010101 (0x15) SPORT3_FS_PBEN_O SPORT 3 Frame Sync Output Enable
010110 (0x16) SPORT3_DA_PBEN_O SPORT 3 Data Channel A Output Enable
010111 (0x17) SPORT3_DB_PBEN_O SPORT 3 Data Channel B Output Enable
011000 (0x18) SPORT4_CLK_PBEN_O SPORT 4 Clock Output Enable
011001 (0x19) SPORT4_FS_PBEN_O SPORT 4 Frame Sync Output Enable
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