ADSP-214xx SHARC Processor Hardware Reference xi
Contents
Initialization Time ............................................................ 3-70
Internal DDR2 Bank Access .............................................. 3-71
Single Bank Access ........................................................ 3-71
Multibank Access .......................................................... 3-71
Force Activation Window .............................................. 3-72
Multi Bank Operation with Data Packing ..................... 3-73
Fixed Timing Parameters ............................................... 3-74
Operating Modes ................................................................... 3-75
Parallel Connection of DDR2s .......................................... 3-75
Buffering Controller for Multiple DDR2s ...................... 3-76
Read Optimization ............................................................ 3-76
DDR2 Read Optimization ............................................ 3-77
Self-Refresh Mode ......................................................... 3-79
Single-Ended Data Strobe .............................................. 3-81
On Die Termination (ODT) ......................................... 3-81
Additive Latency ........................................................... 3-82
Forcing DDR2 Commands ........................................... 3-82
Data Transfer .............................................................................. 3-84
Data Buffers .......................................................................... 3-84
AMI Receive Buffer ........................................................... 3-84
AMI Transmit Buffer ........................................................ 3-84
DMA Buffer ..................................................................... 3-85
Core Access ........................................................................... 3-85
External Port Dual Data Fetch ........................................... 3-85
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