Contents
xiv ADSP-214xx SHARC Processor Hardware Reference
Additional Information ................................................... 3-124
AMI Initialization .......................................................... 3-125
SDRAM Controller ............................................................. 3-126
Power-Up Sequence ........................................................ 3-126
Output Clock Generator Programming Model ................ 3-127
Self-Refresh Mode .......................................................... 3-127
Changing the VCO Clock During Runtime ................... 3-128
DDR2 Controller ............................................................... 3-129
Power-Up Sequence ........................................................ 3-129
Frequency Change in Precharge Power-Down Mode ........ 3-130
External Instruction Fetch ................................................... 3-131
AMI Configuration ........................................................ 3-132
SDRAM Configuration .................................................. 3-132
External Memory Access Restrictions ................................... 3-132
LINK PORTS—ADSP-2146X
Features ........................................................................................ 4-2
Pin Descriptions ........................................................................... 4-3
Register Overview ......................................................................... 4-3
Clocking ...................................................................................... 4-4
Functional Description ................................................................. 4-4
Architecture ............................................................................ 4-5
Protocol .................................................................................. 4-5
Intercommunication ............................................................... 4-7
Self-Synchronization ............................................................. 4-10
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