Peripheral Registers
A-104 ADSP-214xx SHARC Processor Hardware Reference
20 MASK4 Mask Buffer Error. When set, masks buffer error channel interrupts
for this logical channel.
21 Reserved
22 MASK6 Mask Lost Frame Synchronization. When set, masks lost frame syn-
chronization channel interrupts for this logical channel.
23 MASK7 Reserved
24 Reserved
26–25 MDS Channel x Mode Select.
00 = Ping-pong DMA mode (default)
01 = Circular buffering DMA
10 = I/O mode enable
11 = Reserved
27 PCE Packet Count Enable. Enable the Rx packet counter. This bit is valid
for asynchronous and control Rx channels in I/O mode.
0 = Disable
1 = Enable
29–28 CTYPE Channel x Type Select.
00 = Synchronous (default)
01 = Reserved
10 = Asynchronous
11 = Control
30 CTRAN Channel x Transmit Select.
0 = Receive (default)
1 = Transmit
31 CE Channel x Enable.
0 = Channel n disabled (default)
1 = Enabled
Table A-66. MLB_CECRx Register Bit Descriptions for Asynchronous
and Control Channels (RW) (Cont’d)
Bit Name Description
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