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EDMA3 Registers
11.4.2.5.3 Error Clear Register (ERRCLR)
The error clear register (ERRCLR) is shown in Figure 11-111 and described in Table 11-96.
Figure 11-111. Error Clear Register (ERRCLR)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved MMRAERR TRERR Reserved BUSERR
R-0 W-0 W-0 R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 11-96. Error Clear Register (ERRCLR) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
3 MMRAERR Interrupt enable clear for the MMRAERR bit in the error status register (ERRSTAT).
0 No effect.
1 Clears the MMRAERR bit in ERRSTAT but does not clear the error details register (ERRDET).
2 TRERR Interrupt enable clear for the TRERR bit in the error status register (ERRSTAT).
0 No effect.
1 Clears the TRERR bit in ERRSTAT but does not clear the error details register (ERRDET).
1 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
0 BUSERR Interrupt clear for the BUSERR bit in the error status register (ERRSTAT).
0 No effect.
1 Clears the BUSERR bit in ERRSTAT and clears the error details register (ERRDET).
1001
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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