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Power, Reset, and Clock Management
8.1.12.3.13 CLKSEL_WDT1_CLK Register (offset = 38h) [reset = 1h]
CLKSEL_WDT1_CLK is shown in Figure 8-150 and described in Table 8-159.
Selects the Mux select line for Watchdog1 clock [warm reset insensitive]
Figure 8-150. CLKSEL_WDT1_CLK Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-159. CLKSEL_WDT1_CLK Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 CLKSEL R/W 1h
Selects the Mux select line for WDT1 clock [warm reset insensitive]
0x0 = SEL1 : Select 32KHZ clock from RC Oscillator
0x1 = SEL2 : Select 32KHZ from 32K Clock divider
687
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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